Spread Spectrum Frequency Timing Generator
W42C31-09
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
January 25, 2000, rev. *B
Features
Maximized EMI suppression using Cypress's Spread
Spectrum technology
Generates a spread spectrum copy of the provided
input
Integrated loop filter components
Operates with a 3.3V or 5V supply
Low-power CMOS design
Available in 8-pin SOIC (Small Outline Integrated
Circuit)
Overview
The W42C31-09 incorporates the latest advances in PLL
spread spectrum frequency synthesizer techniques. By fre-
quency modulating the output with a low-frequency carrier,
EMI is greatly reduced. Use of this technology allows systems
to pass increasingly difficult EMI testing without resorting to
costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Table 1. Frequency Spread Selection
W42C31-09
Input Frequency
(MHz)
Output Frequency
(MHz)
FS1
FS0
0
0
30 to 55
f
IN
0.625%
0
1
30 to 55
f
IN
1.25%
1
0
30 to 55
f
IN
2.5%
1
1
30 to 55
f
IN
3.75%
Simplified Block Diagram
Pin Configuration
SOIC
Oscillator or Reference
Spread Spectrum
W42C31-09
(EMI suppressed)
VDD
Input
Output
W4
2
C
3
1
-
0
9
8
7
6
5
1
2
3
4
CLKIN
NC
GND
FS1
SSON#
CLKOUT
FS0
VDD
W42C31-09
2
Functional Description
The W42C31-09 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W42C31-09 the
output frequency is equal to the input frequency.) The unique
feature of the Spread Spectrum Frequency Timing Generator
is that a modulating waveform is superimposed at the input to
the VCO. This causes the VCO output to be slowly swept
across a predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed, the modula-
tion percentage may be varied.
Using frequency select bits (FS1:0 pins), various spreading
percentages can be chosen (see Table 1).
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between 0.5% and 2.5% are most
common.
The W42C31 features the ability to select from various spread
spectrum characteristics. Selections specific to the
W42C31-09 are shown in Table 1. Other spreading character-
istics are available (see separate data sheets) or can be cre-
ated with a custom mask. Also, other devices in the W42C31
family offer frequency multiplication in addition to the spread
spectrum function. This will allow the use of less expensive
fundamental mode crystals.
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
CLKOUT
7
O
Output Modulated Frequency: Frequency modulated copy of the unmodulated input
clock.
CLKIN
1
I
External Reference Frequency Input
NC
2
I
No Connect: This pin must be left unconnected.
SSON#
8
I
Spread Spectrum Control (Active LOW): Pulling this input signal LOW turns the
internal modulation waveform on. This pin has an internal pull-down resistor.
FS0:1
6, 4
I
Frequency Selection Bit 0: These pins select the frequency spreading
characteristics. Refer to Table 1. These pins have internal pull-up resistors.
VDD
5
P
Power Connection: Connected to 3.3V or 5V power supply.
GND
3
G
Ground Connection: This should be connected to the common ground plane.
Figure 1. System Block Diagram (Concept, not actual implementation)
Freq.
Phase
Modulating
VCO
Post
CLKOUT
Detector
Charge
Pump
Waveform
Dividers
Divider
Feedback
Divider
PLL
GND
VDD
Q
P
Clock Input
Reference Input
(EMI suppressed)
W42C31-09
3
Spread Spectrum Frequency Timing
Generation
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.
Contrast the typical clock EMI with the Cypress Spread Spec-
trum Frequency Timing Generation EMI. Notice the spike in
the typical clock. This spike can make systems fail quasi-peak
EMI testing. The FCC and other regulatory agencies test for
peak emissions. With spread spectrum enabled, the peak en-
ergy is much lower (at least 8 dB) because the energy is
spread out across a wider bandwidth.
Modulating Waveform
The shape of the modulating waveform is critical to EMI reduc-
tion. The modulation scheme used to accomplish the maxi-
mum reduction in EMI is shown in Figure 3. The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the spread-
ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This method is always shown using the expression
f
Center
X
MOD
% in the frequency spread selection table.
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this fre-
quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap-
proach is f
MAX
X
MOD
%. Whenever this expression is used,
Cypress has taken care to ensure that f
MAX
will never be ex-
ceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
SSON# Pin
An internal pull-down resistor defaults the chip into a spread
spectrum mode. The SSON# pin enables the spreading fea-
ture when set LOW. The SSON# pin disables the spreading
feature when set HIGH (V
DD
).
S S FT G
Typ ical C lo ck
F req uen cy S p an (M H z )
-S S %
+ S S %
A
m
p
lit
u
d
e
(
d
B
)
5 d B /d iv
Spread
Spectrum
Enabled
EMI Reduction
Spread
Spectrum
Non-
Figure 2. Typical Clock and SSFTG Comparison
100%
60%
20%
80%
40%
0%
20%
40%
60%
80%
100%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
Time
Fr
e
q
ue
nc
y
S
h
i
f
t
Figure 3. Modulation Waveform Profile
W42C31-09
4
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
Description
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +70
C
T
B
Ambient Temperature under Bias
55 to +125
C
P
D
Power Dissipation
0.5
W
DC Electrical Characteristics:
0C < T
A
< 70C, V
DD
= 3.3V 10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
I
DD
Supply Current
18
32
mA
t
ON
Power Up Time
First locked clock cycle after
Power Good
5
ms
V
IL
(Logic Inputs)
Input Low Voltage
0.8
V
V
IL
(CLKIN)
Input Low Voltage
.4
V
V
IH
(Logic Inputs)
Input High Voltage
2.4
V
V
IH
(CLKIN)
Input High Voltage
2.8
V
V
OL
Output Low Voltage
I
OL
= 21.6 mA
[1]
0.4
V
V
OH
Output High Voltage
I
OH
= 31.5 mA
[1]
2.5
V
I
IL
Input Low Current
Note 2
100
A
I
IH
Input High Current
Note 2
10
A
I
OL
Output Low Current
@ 0.4V, V
DD
= 3.3V
15
mA
I
OH
Output High Current
@ 2.4V, V
DD
= 3.3V
15
mA
C
I
Input Capacitance
All pins except CLKIN
7
pF
C
I
Input Capacitance
CLKIN pin only
6
10
pF
R
P
Input Pull-Up Resistor
500
k
Z
OUT
Clock Output Impedance
25
Notes:
1.
Output driver is full CMOS.
2.
Inputs FS1:0 have a pull-up resistor, Input SSON# has a pull-down resistor.
W42C31-09
5
DC Electrical Characteristics:
0C < T
A
< 70C, V
DD
= 5V 10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
I
DD
Supply Current
30
45
mA
t
ON
Power Up Time
First locked clock cycle after
Power Good
5
ms
V
IL
(Logic Inputs)
Input Low Voltage
0.15V
DD
V
V
IL
(CLKIN)
Input Low Voltage
0.4
V
V
IH
(Logic Inputs)
Input High Voltage
0.7V
DD
V
V
IH
(CLKIN)
Input High Voltage
4.2
V
V
OL
Output Low Voltage
I
OL
= 25.7mA
0.4
V
V
OH
Output High Voltage
I
OH
= 118.mA
2.5
V
I
IL
Input Low Current
Note 2
100
A
I
IH
Input High Current
Note 2
10
A
I
OL
Output Low Current
@ 0.4V, V
DD
= 5V
24
mA
I
OH
Output High Current
@ 2.4V, V
DD
= 5V
24
mA
C
I
Input Capacitance
All pins except CLKIN
7
pF
C
I
Input Capacitance
CLKIN pin only
6
10
pF
R
P
Input Pull-Up Resistor
500
k
Z
OUT
Clock Output Impedance
25
AC Electrical Characteristics:
T
A
= 0C to +70C, V
DD
= 3.3V10%
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
f
IN
Input Frequency
Input Clock
30
40
55
MHz
f
OUT
Output Frequency
Spread Off
30
40
55
MHz
t
R
Output Rise Time
V, 15-pF load 0.8 2.4
2
5
ns
t
F
Output Fall Time
V, 15-pF load 2.4 0.8
2
5
ns
t
OD
Output Duty Cycle
15-pF load
40
60
%
t
ID
Input Duty Cycle
40
60
%
t
JCYC
Jitter, Cycle-to-Cycle
250
300
ps
Harmonic Reduction
f
out
= 40 MHz, third harmonic
measured, reference board,
15-pF load
8
dB
AC Electrical Characteristics:
T
A
= 0C to +70C, V
DD
= 5V10%
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
f
IN
Input Frequency
Input Clock
30
40
55
MHz
f
OUT
Output Frequency
Spread Off
30
40
55
MHz
t
R
Output Rise Time
V, 15-pF load 0.8 2.4
2
5
ns
t
F
Output Fall Time
V, 15-pF load 2.4 0.8
2
5
ns
t
OD
Output Duty Cycle
15-pF load
40
60
%
t
ID
Input Duty Cycle
40
60
%
t
JCYC
Jitter, Cycle-to-Cycle
250
300
ps
Harmonic Reduction
f
out
= 40 MHz, third harmonic
measured, reference board,
15-pF load
8
dB
W42C31-09
6
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
V
DD
decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-
F decoupling capacitor should be
placed as close to the V
DD
pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-
F decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V
DD
connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5 shows a recommended 2-layer board layout.
Document #: 38-00799-B
Figure 4. Recommended Circuit Configuration
GND
W4
2
C
3
1
-0
9
8
7
6
5
1
2
3
4
R1
C1
FB
C2
5V or 3.3V System Supply
10 F Tantalum
VDD
0.1 F
Clock Output
Reference Input
NC
Ordering Information
Ordering Code
Freq. Mask
Code
Package
Name
Package Type
W42C31
09
G
8-pin Plastic SOIC (150-mil)
Figure 5. Recommended Board Layout (2-Layer Board)
Clock Output
High frequency supply decoupling
capacitor (0.1-F recommended).
Common supply low frequency
decoupling capacitor (10-F tantalum
recommended).
FB
Ferrite Bead
C1 =
C2 =
Match value to line impedance
R1 =
=
R1
C1
C2
G
G
FB
Power Supply Input
(3.3V or 5V)
=
Via To GND Plane
G
Reference Input
NC
G
W42C31-09
Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
8-Pin Small Outline Integrated Circuit (SOIC, 150-mil)
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